// +FHDR============================================================================/
// Author       : hjie
// Creat Time   : 2025/03/18 11:20:38
// File Name    : sim_examp_axi_ddr4_top.v
// Module Ver   : Vx.x
//
//
// All Rights Reserved
//
// ---------------------------------------------------------------------------------/
//
// Modification History:
// V1.0         initial
//
// -FHDR============================================================================/
// 
// sim_examp_axi_ddr4_top
//    |---
// 
`timescale 1ns/1ps

module sim_examp_axi_ddr4_top #
(
    parameter                           U_DLY = 1                     // 
)
(
// ---------------------------------------------------------------------------------
// CLock & Reset
// ---------------------------------------------------------------------------------
    input                               clk_40m                     , 
    input                               rst_sys_n                   , 

    input                               clk_ddr0_p                  , 
    input                               clk_ddr0_n                  , 
    input                               clk_ddr1_p                  , 
    input                               clk_ddr1_n                  , 
// ---------------------------------------------------------------------------------
// AXI4
// ---------------------------------------------------------------------------------
    input                               axi4_s0_clk                 , 
    input                               axi4_s0_rst_n               , 

    input                         [3:0] axi4_s0_awid                , 
    input                        [31:0] axi4_s0_awaddr              , 
    input                         [7:0] axi4_s0_awlen               , 
    input                         [1:0] axi4_s0_awburst             , 
    input                         [2:0] axi4_s0_awsize              , 
    output                              axi4_s0_awready             , 
    input                               axi4_s0_awvalid             , 

    input                       [127:0] axi4_s0_wdata               , 
    input                        [15:0] axi4_s0_wstrb               , 
    input                               axi4_s0_wlast               , 
    output                              axi4_s0_wready              , 
    input                               axi4_s0_wvalid              , 

    output                        [3:0] axi4_s0_bid                 , 
    output                        [1:0] axi4_s0_bresp               , 
    input                               axi4_s0_bready              , 
    output                              axi4_s0_bvalid              , 

    input                         [3:0] axi4_s0_arid                , 
    input                        [31:0] axi4_s0_araddr              , 
    input                         [7:0] axi4_s0_arlen               , 
    input                         [1:0] axi4_s0_arburst             , 
    input                         [2:0] axi4_s0_arsize              , 
    output                              axi4_s0_arready             , 
    input                               axi4_s0_arvalid             , 

    output                        [3:0] axi4_s0_rid                 , 
    output                      [127:0] axi4_s0_rdata               , 
    output                        [1:0] axi4_s0_rresp               , 
    output                              axi4_s0_rlast               , 
    input                               axi4_s0_rready              , 
    output                              axi4_s0_rvalid              , 
// ---------------------------------------------------------------------------------
// DDR4 CH0
// ---------------------------------------------------------------------------------
    output                       [16:0] ddr4_ch0_addr               , 
    output                        [1:0] ddr4_ch0_ba                 , 
    output                              ddr4_ch0_bg                 , 
    output                              ddr4_ch0_cke                , 
    output                              ddr4_ch0_ck_p               , 
    output                              ddr4_ch0_ck_n               , 
    output                              ddr4_ch0_reset_n            , 
    output                              ddr4_ch0_cs_n               , 
    inout                        [63:0] ddr4_ch0_dq                 , 
    inout                         [7:0] ddr4_ch0_dqs_p              , 
    inout                         [7:0] ddr4_ch0_dqs_n              , 
    inout                         [7:0] ddr4_ch0_dm_dbi_n           , 
    output                              ddr4_ch0_odt                , 
    output                              ddr4_ch0_act_n              , 
    output                              ddr4_ch0_ten                , 
    output                              ddr4_ch0_par                , 
// ---------------------------------------------------------------------------------
// DDR4 CH1
// ---------------------------------------------------------------------------------
    output                       [16:0] ddr4_ch1_addr               , 
    output                        [1:0] ddr4_ch1_ba                 , 
    output                              ddr4_ch1_bg                 , 
    output                              ddr4_ch1_cke                , 
    output                              ddr4_ch1_ck_p               , 
    output                              ddr4_ch1_ck_n               , 
    output                              ddr4_ch1_reset_n            , 
    output                              ddr4_ch1_cs_n               , 
    inout                        [63:0] ddr4_ch1_dq                 , 
    inout                         [7:0] ddr4_ch1_dqs_p              , 
    inout                         [7:0] ddr4_ch1_dqs_n              , 
    inout                         [7:0] ddr4_ch1_dm_dbi_n           , 
    output                              ddr4_ch1_odt                , 
    output                              ddr4_ch1_act_n              , 
    output                              ddr4_ch1_ten                , 
    output                              ddr4_ch1_par                  
);

wire                                    clk_100m_g                  ; 
wire                                    rst_n                       ; 

wire                                    clk_ddr0                    ; 
wire                                    rst_ddr0                    ; 
wire                                    clk_ddr1                    ; 
wire                                    rst_ddr1                    ; 


wire                             [31:0] axi4_m0_araddr              ; 
wire                              [1:0] axi4_m0_arburst             ; 
wire                              [7:0] axi4_m0_arlen               ; 
wire                              [2:0] axi4_m0_arsize              ; 
wire                                    axi4_m0_arready             ; 
wire                                    axi4_m0_arvalid             ; 

wire                            [255:0] axi4_m0_rdata               ; 
wire                                    axi4_m0_rlast               ; 
wire                                    axi4_m0_rready              ; 
wire                              [1:0] axi4_m0_rresp               ; 
wire                                    axi4_m0_rvalid              ; 

wire                             [31:0] axi4_m0_awaddr              ; 
wire                              [1:0] axi4_m0_awburst             ; 
wire                              [7:0] axi4_m0_awlen               ; 
wire                              [2:0] axi4_m0_awsize              ; 
wire                                    axi4_m0_awready             ; 
wire                                    axi4_m0_awvalid             ; 

wire                            [255:0] axi4_m0_wdata               ; 
wire                                    axi4_m0_wlast               ; 
wire                                    axi4_m0_wready              ; 
wire                             [31:0] axi4_m0_wstrb               ; 
wire                                    axi4_m0_wvalid              ; 

wire                                    axi4_m0_bready              ; 
wire                              [1:0] axi4_m0_bresp               ; 
wire                                    axi4_m0_bvalid              ; 


wire                             [31:0] axi4_m1_araddr              ; 
wire                              [1:0] axi4_m1_arburst             ; 
wire                              [7:0] axi4_m1_arlen               ; 
wire                              [2:0] axi4_m1_arsize              ; 
wire                                    axi4_m1_arready             ; 
wire                                    axi4_m1_arvalid             ; 

wire                            [255:0] axi4_m1_rdata               ; 
wire                                    axi4_m1_rlast               ; 
wire                                    axi4_m1_rready              ; 
wire                              [1:0] axi4_m1_rresp               ; 
wire                                    axi4_m1_rvalid              ; 

wire                             [31:0] axi4_m1_awaddr              ; 
wire                              [1:0] axi4_m1_awburst             ; 
wire                              [7:0] axi4_m1_awlen               ; 
wire                              [2:0] axi4_m1_awsize              ; 
wire                                    axi4_m1_awready             ; 
wire                                    axi4_m1_awvalid             ; 

wire                            [255:0] axi4_m1_wdata               ; 
wire                                    axi4_m1_wlast               ; 
wire                                    axi4_m1_wready              ; 
wire                             [31:0] axi4_m1_wstrb               ; 
wire                                    axi4_m1_wvalid              ; 

wire                                    axi4_m1_bready              ; 
wire                              [1:0] axi4_m1_bresp               ; 
wire                                    axi4_m1_bvalid              ; 


wire                             [31:0] axi4_m2_araddr              ; 
wire                              [1:0] axi4_m2_arburst             ; 
wire                              [7:0] axi4_m2_arlen               ; 
wire                              [2:0] axi4_m2_arsize              ; 
wire                                    axi4_m2_arready             ; 
wire                                    axi4_m2_arvalid             ; 

wire                             [31:0] axi4_m2_rdata               ; 
wire                                    axi4_m2_rlast               ; 
wire                                    axi4_m2_rready              ; 
wire                              [1:0] axi4_m2_rresp               ; 
wire                                    axi4_m2_rvalid              ; 

wire                             [31:0] axi4_m2_awaddr              ; 
wire                              [1:0] axi4_m2_awburst             ; 
wire                              [7:0] axi4_m2_awlen               ; 
wire                              [2:0] axi4_m2_awsize              ; 
wire                                    axi4_m2_awready             ; 
wire                                    axi4_m2_awvalid             ; 

wire                             [31:0] axi4_m2_wdata               ; 
wire                                    axi4_m2_wlast               ; 
wire                                    axi4_m2_wready              ; 
wire                              [3:0] axi4_m2_wstrb               ; 
wire                                    axi4_m2_wvalid              ; 

wire                                    axi4_m2_bready              ; 
wire                              [1:0] axi4_m2_bresp               ; 
wire                                    axi4_m2_bvalid              ; 

clk_top u0_clk_top
(
// Clock out ports
    .clk_out1                       (clk_100m_g                 ), // output clk_out1
    .clk_out2                       (                           ), // output clk_out2
// Status and control signals
    .resetn                         (rst_sys_n                  ), // input resetn
    .locked                         (rst_n                      ), // output locked
// Clock in ports
    .clk_in1                        (clk_40m                    )  // input clk_in1
);

bd_top u0_bd_top
(
    .clk_axi_m0                     (clk_ddr0                   ), 
    .clk_axi_m1                     (clk_ddr1                   ), 
    .clk_axi_m2                     (clk_100m_g                 ), 
    .clk_axi_s0                     (axi4_s0_clk                ), 
    .rst_axi4_m0_n                  (~rst_ddr0                  ), 
    .rst_axi4_m1_n                  (~rst_ddr1                  ), 
    .rst_axi4_m2_n                  (rst_n                      ), 
    .rst_axi4_s0_n                  (axi4_s0_rst_n              ), 

    .S00_AXI_0_arid                 (axi4_s0_arid               ), 
    .S00_AXI_0_araddr               (axi4_s0_araddr             ), 
    .S00_AXI_0_arburst              (axi4_s0_arburst            ), 
    .S00_AXI_0_arlen                (axi4_s0_arlen              ), 
    .S00_AXI_0_arsize               (axi4_s0_arsize             ), 
    .S00_AXI_0_arready              (axi4_s0_arready            ), 
    .S00_AXI_0_arvalid              (axi4_s0_arvalid            ), 
    .S00_AXI_0_arcache              ('d0                        ), 
    .S00_AXI_0_arlock               ('d0                        ), 
    .S00_AXI_0_arprot               ('d0                        ), 
    .S00_AXI_0_arqos                ('d0                        ), 
    .S00_AXI_0_arregion             ('d0                        ), 

    .S00_AXI_0_rdata                (axi4_s0_rdata              ), 
    .S00_AXI_0_rid                  (axi4_s0_rid                ), 
    .S00_AXI_0_rlast                (axi4_s0_rlast              ), 
    .S00_AXI_0_rready               (axi4_s0_rready             ), 
    .S00_AXI_0_rresp                (axi4_s0_rresp              ), 
    .S00_AXI_0_rvalid               (axi4_s0_rvalid             ), 

    .S00_AXI_0_awid                 (axi4_s0_awid               ), 
    .S00_AXI_0_awaddr               (axi4_s0_awaddr             ), 
    .S00_AXI_0_awburst              (axi4_s0_awburst            ), 
    .S00_AXI_0_awlen                (axi4_s0_awlen              ), 
    .S00_AXI_0_awsize               (axi4_s0_awsize             ), 
    .S00_AXI_0_awready              (axi4_s0_awready            ), 
    .S00_AXI_0_awvalid              (axi4_s0_awvalid            ), 
    .S00_AXI_0_awcache              ('d0                        ), 
    .S00_AXI_0_awlock               ('d0                        ), 
    .S00_AXI_0_awprot               ('d0                        ), 
    .S00_AXI_0_awqos                ('d0                        ), 
    .S00_AXI_0_awregion             ('d0                        ), 

    .S00_AXI_0_wdata                (axi4_s0_wdata              ), 
    .S00_AXI_0_wlast                (axi4_s0_wlast              ), 
    .S00_AXI_0_wready               (axi4_s0_wready             ), 
    .S00_AXI_0_wstrb                (axi4_s0_wstrb              ), 
    .S00_AXI_0_wvalid               (axi4_s0_wvalid             ), 

    .S00_AXI_0_bid                  (axi4_s0_bid                ), 
    .S00_AXI_0_bready               (axi4_s0_bready             ), 
    .S00_AXI_0_bresp                (axi4_s0_bresp              ), 
    .S00_AXI_0_bvalid               (axi4_s0_bvalid             ), 


    .M00_AXI_0_araddr               (axi4_m0_araddr             ), 
    .M00_AXI_0_arburst              (axi4_m0_arburst            ), 
    .M00_AXI_0_arcache              (                           ), 
    .M00_AXI_0_arlen                (axi4_m0_arlen              ), 
    .M00_AXI_0_arlock               (                           ), 
    .M00_AXI_0_arprot               (                           ), 
    .M00_AXI_0_arqos                (                           ), 
    .M00_AXI_0_arready              (axi4_m0_arready            ), 
    .M00_AXI_0_arregion             (                           ), 
    .M00_AXI_0_arsize               (axi4_m0_arsize             ), 
    .M00_AXI_0_arvalid              (axi4_m0_arvalid            ), 

    .M00_AXI_0_rdata                (axi4_m0_rdata              ), 
    .M00_AXI_0_rlast                (axi4_m0_rlast              ), 
    .M00_AXI_0_rready               (axi4_m0_rready             ), 
    .M00_AXI_0_rresp                (axi4_m0_rresp              ), 
    .M00_AXI_0_rvalid               (axi4_m0_rvalid             ), 

    .M00_AXI_0_awaddr               (axi4_m0_awaddr             ), 
    .M00_AXI_0_awburst              (axi4_m0_awburst            ), 
    .M00_AXI_0_awcache              (                           ), 
    .M00_AXI_0_awlen                (axi4_m0_awlen              ), 
    .M00_AXI_0_awlock               (                           ), 
    .M00_AXI_0_awprot               (                           ), 
    .M00_AXI_0_awqos                (                           ), 
    .M00_AXI_0_awready              (axi4_m0_awready            ), 
    .M00_AXI_0_awregion             (                           ), 
    .M00_AXI_0_awsize               (axi4_m0_awsize             ), 
    .M00_AXI_0_awvalid              (axi4_m0_awvalid            ), 

    .M00_AXI_0_bready               (axi4_m0_bready             ), 
    .M00_AXI_0_bresp                (axi4_m0_bresp              ), 
    .M00_AXI_0_bvalid               (axi4_m0_bvalid             ), 

    .M00_AXI_0_wdata                (axi4_m0_wdata              ), 
    .M00_AXI_0_wlast                (axi4_m0_wlast              ), 
    .M00_AXI_0_wready               (axi4_m0_wready             ), 
    .M00_AXI_0_wstrb                (axi4_m0_wstrb              ), 
    .M00_AXI_0_wvalid               (axi4_m0_wvalid             ), 


    .M01_AXI_0_araddr               (axi4_m1_araddr             ), 
    .M01_AXI_0_arburst              (axi4_m1_arburst            ), 
    .M01_AXI_0_arcache              (                           ), 
    .M01_AXI_0_arlen                (axi4_m1_arlen              ), 
    .M01_AXI_0_arlock               (                           ), 
    .M01_AXI_0_arprot               (                           ), 
    .M01_AXI_0_arqos                (                           ), 
    .M01_AXI_0_arready              (axi4_m1_arready            ), 
    .M01_AXI_0_arregion             (                           ), 
    .M01_AXI_0_arsize               (axi4_m1_arsize             ), 
    .M01_AXI_0_arvalid              (axi4_m1_arvalid            ), 

    .M01_AXI_0_rdata                (axi4_m1_rdata              ), 
    .M01_AXI_0_rlast                (axi4_m1_rlast              ), 
    .M01_AXI_0_rready               (axi4_m1_rready             ), 
    .M01_AXI_0_rresp                (axi4_m1_rresp              ), 
    .M01_AXI_0_rvalid               (axi4_m1_rvalid             ), 

    .M01_AXI_0_awaddr               (axi4_m1_awaddr             ), 
    .M01_AXI_0_awburst              (axi4_m1_awburst            ), 
    .M01_AXI_0_awcache              (                           ), 
    .M01_AXI_0_awlen                (axi4_m1_awlen              ), 
    .M01_AXI_0_awlock               (                           ), 
    .M01_AXI_0_awprot               (                           ), 
    .M01_AXI_0_awqos                (                           ), 
    .M01_AXI_0_awready              (axi4_m1_awready            ), 
    .M01_AXI_0_awregion             (                           ), 
    .M01_AXI_0_awsize               (axi4_m1_awsize             ), 
    .M01_AXI_0_awvalid              (axi4_m1_awvalid            ), 

    .M01_AXI_0_bready               (axi4_m1_bready             ), 
    .M01_AXI_0_bresp                (axi4_m1_bresp              ), 
    .M01_AXI_0_bvalid               (axi4_m1_bvalid             ), 

    .M01_AXI_0_wdata                (axi4_m1_wdata              ), 
    .M01_AXI_0_wlast                (axi4_m1_wlast              ), 
    .M01_AXI_0_wready               (axi4_m1_wready             ), 
    .M01_AXI_0_wstrb                (axi4_m1_wstrb              ), 
    .M01_AXI_0_wvalid               (axi4_m1_wvalid             ), 

    .M02_AXI_0_araddr               (axi4_m2_araddr             ), 
    .M02_AXI_0_arburst              (axi4_m2_arburst            ), 
    .M02_AXI_0_arcache              (                           ), 
    .M02_AXI_0_arlen                (axi4_m2_arlen              ), 
    .M02_AXI_0_arlock               (                           ), 
    .M02_AXI_0_arprot               (                           ), 
    .M02_AXI_0_arqos                (                           ), 
    .M02_AXI_0_arready              (axi4_m2_arready            ), 
    .M02_AXI_0_arregion             (                           ), 
    .M02_AXI_0_arsize               (axi4_m2_arsize             ), 
    .M02_AXI_0_arvalid              (axi4_m2_arvalid            ), 

    .M02_AXI_0_rdata                (axi4_m2_rdata              ), 
    .M02_AXI_0_rlast                (axi4_m2_rlast              ), 
    .M02_AXI_0_rready               (axi4_m2_rready             ), 
    .M02_AXI_0_rresp                (axi4_m2_rresp              ), 
    .M02_AXI_0_rvalid               (axi4_m2_rvalid             ), 

    .M02_AXI_0_awaddr               (axi4_m2_awaddr             ), 
    .M02_AXI_0_awburst              (axi4_m2_awburst            ), 
    .M02_AXI_0_awcache              (                           ), 
    .M02_AXI_0_awlen                (axi4_m2_awlen              ), 
    .M02_AXI_0_awlock               (                           ), 
    .M02_AXI_0_awprot               (                           ), 
    .M02_AXI_0_awqos                (                           ), 
    .M02_AXI_0_awready              (axi4_m2_awready            ), 
    .M02_AXI_0_awregion             (                           ), 
    .M02_AXI_0_awsize               (axi4_m2_awsize             ), 
    .M02_AXI_0_awvalid              (axi4_m2_awvalid            ), 

    .M02_AXI_0_bready               (axi4_m2_bready             ), 
    .M02_AXI_0_bresp                (axi4_m2_bresp              ), 
    .M02_AXI_0_bvalid               (axi4_m2_bvalid             ), 

    .M02_AXI_0_wdata                (axi4_m2_wdata              ), 
    .M02_AXI_0_wlast                (axi4_m2_wlast              ), 
    .M02_AXI_0_wready               (axi4_m2_wready             ), 
    .M02_AXI_0_wstrb                (axi4_m2_wstrb              ), 
    .M02_AXI_0_wvalid               (axi4_m2_wvalid             )  
);

ddr4_0 u0_ddr4_0
(
    .c0_sys_clk_p                   (clk_ddr0_p                 ), // input wire c0_sys_clk_p
    .c0_sys_clk_n                   (clk_ddr0_n                 ), // input wire c0_sys_clk_n

    .sys_rst                        (~rst_sys_n                 ), // input wire sys_rst
    .c0_init_calib_complete         (                           ), // output wire c0_init_calib_complete
    .c0_ddr4_aresetn                (~rst_ddr0                  ), // input wire c0_ddr4_aresetn

    .c0_ddr4_ui_clk                 (clk_ddr0                   ), // output wire c0_ddr4_ui_clk
    .c0_ddr4_ui_clk_sync_rst        (rst_ddr0                   ), // output wire c0_ddr4_ui_clk_sync_rst

    .dbg_clk                        (                           ), // output wire dbg_clk
    .dbg_bus                        (                           ), // output wire [511 : 0] dbg_bus

    .c0_ddr4_adr                    (ddr4_ch0_addr              ), // output wire [16 : 0] c0_ddr4_adr
    .c0_ddr4_ba                     (ddr4_ch0_ba                ), // output wire [1 : 0] c0_ddr4_ba
    .c0_ddr4_bg                     (ddr4_ch0_bg                ), // output wire [0 : 0] c0_ddr4_bg
    .c0_ddr4_cke                    (ddr4_ch0_cke               ), // output wire [0 : 0] c0_ddr4_cke
    .c0_ddr4_ck_t                   (ddr4_ch0_ck_p              ), // output wire [0 : 0] c0_ddr4_ck_t
    .c0_ddr4_ck_c                   (ddr4_ch0_ck_n              ), // output wire [0 : 0] c0_ddr4_ck_c
    .c0_ddr4_reset_n                (ddr4_ch0_reset_n           ), // output wire c0_ddr4_reset_n
    .c0_ddr4_cs_n                   (ddr4_ch0_cs_n              ), // output wire [0 : 0] c0_ddr4_cs_n
    .c0_ddr4_dq                     (ddr4_ch0_dq                ), // inout wire [63 : 0] c0_ddr4_dq
    .c0_ddr4_dqs_t                  (ddr4_ch0_dqs_p             ), // inout wire [7 : 0] c0_ddr4_dqs_t
    .c0_ddr4_dqs_c                  (ddr4_ch0_dqs_n             ), // inout wire [7 : 0] c0_ddr4_dqs_c
    .c0_ddr4_dm_dbi_n               (ddr4_ch0_dm_dbi_n          ), // inout wire [7 : 0] c0_ddr4_dm_dbi_n
    .c0_ddr4_odt                    (ddr4_ch0_odt               ), // output wire [0 : 0] c0_ddr4_odt
    .c0_ddr4_act_n                  (ddr4_ch0_act_n             ), // output wire c0_ddr4_act_n


    .c0_ddr4_s_axi_arid             ('d0                        ), // input wire [3 : 0] c0_ddr4_s_axi_arid
    .c0_ddr4_s_axi_araddr           (axi4_m0_araddr             ), // input wire [30 : 0] c0_ddr4_s_axi_araddr
    .c0_ddr4_s_axi_arlen            (axi4_m0_arlen              ), // input wire [7 : 0] c0_ddr4_s_axi_arlen
    .c0_ddr4_s_axi_arsize           (axi4_m0_arsize             ), // input wire [2 : 0] c0_ddr4_s_axi_arsize
    .c0_ddr4_s_axi_arburst          (axi4_m0_arburst            ), // input wire [1 : 0] c0_ddr4_s_axi_arburst
    .c0_ddr4_s_axi_arlock           ('d0                        ), // input wire [0 : 0] c0_ddr4_s_axi_arlock
    .c0_ddr4_s_axi_arcache          ('d0                        ), // input wire [3 : 0] c0_ddr4_s_axi_arcache
    .c0_ddr4_s_axi_arprot           ('d0                        ), // input wire [2 : 0] c0_ddr4_s_axi_arprot
    .c0_ddr4_s_axi_arqos            ('d0                        ), // input wire [3 : 0] c0_ddr4_s_axi_arqos
    .c0_ddr4_s_axi_arvalid          (axi4_m0_arvalid            ), // input wire c0_ddr4_s_axi_arvalid
    .c0_ddr4_s_axi_arready          (axi4_m0_arready            ), // output wire c0_ddr4_s_axi_arready

    .c0_ddr4_s_axi_rready           (axi4_m0_rready             ), // input wire c0_ddr4_s_axi_rready
    .c0_ddr4_s_axi_rlast            (axi4_m0_rlast              ), // output wire c0_ddr4_s_axi_rlast
    .c0_ddr4_s_axi_rvalid           (axi4_m0_rvalid             ), // output wire c0_ddr4_s_axi_rvalid
    .c0_ddr4_s_axi_rresp            (axi4_m0_rresp              ), // output wire [1 : 0] c0_ddr4_s_axi_rresp
    .c0_ddr4_s_axi_rid              (                           ), // output wire [3 : 0] c0_ddr4_s_axi_rid
    .c0_ddr4_s_axi_rdata            (axi4_m0_rdata              ), // output wire [511 : 0] c0_ddr4_s_axi_rdata

    .c0_ddr4_s_axi_awid             ('d0                        ), // input wire [3 : 0] c0_ddr4_s_axi_awid
    .c0_ddr4_s_axi_awaddr           (axi4_m0_awaddr             ), // input wire [30 : 0] c0_ddr4_s_axi_awaddr
    .c0_ddr4_s_axi_awlen            (axi4_m0_awlen              ), // input wire [7 : 0] c0_ddr4_s_axi_awlen
    .c0_ddr4_s_axi_awsize           (axi4_m0_awsize             ), // input wire [2 : 0] c0_ddr4_s_axi_awsize
    .c0_ddr4_s_axi_awburst          (axi4_m0_awburst            ), // input wire [1 : 0] c0_ddr4_s_axi_awburst
    .c0_ddr4_s_axi_awlock           ('d0                        ), // input wire [0 : 0] c0_ddr4_s_axi_awlock
    .c0_ddr4_s_axi_awcache          ('d0                        ), // input wire [3 : 0] c0_ddr4_s_axi_awcache
    .c0_ddr4_s_axi_awprot           ('d0                        ), // input wire [2 : 0] c0_ddr4_s_axi_awprot
    .c0_ddr4_s_axi_awqos            ('d0                        ), // input wire [3 : 0] c0_ddr4_s_axi_awqos
    .c0_ddr4_s_axi_awvalid          (axi4_m0_awvalid            ), // input wire c0_ddr4_s_axi_awvalid
    .c0_ddr4_s_axi_awready          (axi4_m0_awready            ), // output wire c0_ddr4_s_axi_awready

    .c0_ddr4_s_axi_wdata            (axi4_m0_wdata              ), // input wire [511 : 0] c0_ddr4_s_axi_wdata
    .c0_ddr4_s_axi_wstrb            (axi4_m0_wstrb              ), // input wire [63 : 0] c0_ddr4_s_axi_wstrb
    .c0_ddr4_s_axi_wlast            (axi4_m0_wlast              ), // input wire c0_ddr4_s_axi_wlast
    .c0_ddr4_s_axi_wvalid           (axi4_m0_wvalid             ), // input wire c0_ddr4_s_axi_wvalid
    .c0_ddr4_s_axi_wready           (axi4_m0_wready             ), // output wire c0_ddr4_s_axi_wready

    .c0_ddr4_s_axi_bready           (axi4_m0_bready             ), // input wire c0_ddr4_s_axi_bready
    .c0_ddr4_s_axi_bid              (                           ), // output wire [3 : 0] c0_ddr4_s_axi_bid
    .c0_ddr4_s_axi_bresp            (axi4_m0_bresp              ), // output wire [1 : 0] c0_ddr4_s_axi_bresp
    .c0_ddr4_s_axi_bvalid           (axi4_m0_bvalid             )  // output wire c0_ddr4_s_axi_bvalid
);

ddr4_0 u1_ddr4_0
(
    .c0_sys_clk_p                   (clk_ddr1_p                 ), // input wire c0_sys_clk_p
    .c0_sys_clk_n                   (clk_ddr1_n                 ), // input wire c0_sys_clk_n

    .sys_rst                        (~rst_sys_n                 ), // input wire sys_rst
    .c0_init_calib_complete         (                           ), // output wire c0_init_calib_complete
    .c0_ddr4_aresetn                (~rst_ddr1                  ), // input wire c0_ddr4_aresetn

    .c0_ddr4_ui_clk                 (clk_ddr1                   ), // output wire c0_ddr4_ui_clk
    .c0_ddr4_ui_clk_sync_rst        (rst_ddr1                   ), // output wire c0_ddr4_ui_clk_sync_rst

    .dbg_clk                        (                           ), // output wire dbg_clk
    .dbg_bus                        (                           ), // output wire [511 : 0] dbg_bus

    .c0_ddr4_adr                    (ddr4_ch1_addr              ), // output wire [16 : 0] c0_ddr4_adr
    .c0_ddr4_ba                     (ddr4_ch1_ba                ), // output wire [1 : 0] c0_ddr4_ba
    .c0_ddr4_bg                     (ddr4_ch1_bg                ), // output wire [0 : 0] c0_ddr4_bg
    .c0_ddr4_cke                    (ddr4_ch1_cke               ), // output wire [0 : 0] c0_ddr4_cke
    .c0_ddr4_ck_t                   (ddr4_ch1_ck_p              ), // output wire [0 : 0] c0_ddr4_ck_t
    .c0_ddr4_ck_c                   (ddr4_ch1_ck_n              ), // output wire [0 : 0] c0_ddr4_ck_c
    .c0_ddr4_reset_n                (ddr4_ch1_reset_n           ), // output wire c0_ddr4_reset_n
    .c0_ddr4_cs_n                   (ddr4_ch1_cs_n              ), // output wire [0 : 0] c0_ddr4_cs_n
    .c0_ddr4_dq                     (ddr4_ch1_dq                ), // inout wire [63 : 0] c0_ddr4_dq
    .c0_ddr4_dqs_t                  (ddr4_ch1_dqs_p             ), // inout wire [7 : 0] c0_ddr4_dqs_t
    .c0_ddr4_dqs_c                  (ddr4_ch1_dqs_n             ), // inout wire [7 : 0] c0_ddr4_dqs_c
    .c0_ddr4_dm_dbi_n               (ddr4_ch1_dm_dbi_n          ), // inout wire [7 : 0] c0_ddr4_dm_dbi_n
    .c0_ddr4_odt                    (ddr4_ch1_odt               ), // output wire [0 : 0] c0_ddr4_odt
    .c0_ddr4_act_n                  (ddr4_ch1_act_n             ), // output wire c0_ddr4_act_n


    .c0_ddr4_s_axi_arid             ('d0                        ), // input wire [3 : 0] c0_ddr4_s_axi_arid
    .c0_ddr4_s_axi_araddr           (axi4_m1_araddr             ), // input wire [30 : 0] c0_ddr4_s_axi_araddr
    .c0_ddr4_s_axi_arlen            (axi4_m1_arlen              ), // input wire [7 : 0] c0_ddr4_s_axi_arlen
    .c0_ddr4_s_axi_arsize           (axi4_m1_arsize             ), // input wire [2 : 0] c0_ddr4_s_axi_arsize
    .c0_ddr4_s_axi_arburst          (axi4_m1_arburst            ), // input wire [1 : 0] c0_ddr4_s_axi_arburst
    .c0_ddr4_s_axi_arlock           ('d0                        ), // input wire [0 : 0] c0_ddr4_s_axi_arlock
    .c0_ddr4_s_axi_arcache          ('d0                        ), // input wire [3 : 0] c0_ddr4_s_axi_arcache
    .c0_ddr4_s_axi_arprot           ('d0                        ), // input wire [2 : 0] c0_ddr4_s_axi_arprot
    .c0_ddr4_s_axi_arqos            ('d0                        ), // input wire [3 : 0] c0_ddr4_s_axi_arqos
    .c0_ddr4_s_axi_arvalid          (axi4_m1_arvalid            ), // input wire c0_ddr4_s_axi_arvalid
    .c0_ddr4_s_axi_arready          (axi4_m1_arready            ), // output wire c0_ddr4_s_axi_arready

    .c0_ddr4_s_axi_rready           (axi4_m1_rready             ), // input wire c0_ddr4_s_axi_rready
    .c0_ddr4_s_axi_rlast            (axi4_m1_rlast              ), // output wire c0_ddr4_s_axi_rlast
    .c0_ddr4_s_axi_rvalid           (axi4_m1_rvalid             ), // output wire c0_ddr4_s_axi_rvalid
    .c0_ddr4_s_axi_rresp            (axi4_m1_rresp              ), // output wire [1 : 0] c0_ddr4_s_axi_rresp
    .c0_ddr4_s_axi_rid              (                           ), // output wire [3 : 0] c0_ddr4_s_axi_rid
    .c0_ddr4_s_axi_rdata            (axi4_m1_rdata              ), // output wire [511 : 0] c0_ddr4_s_axi_rdata

    .c0_ddr4_s_axi_awid             ('d0                        ), // input wire [3 : 0] c0_ddr4_s_axi_awid
    .c0_ddr4_s_axi_awaddr           (axi4_m1_awaddr             ), // input wire [30 : 0] c0_ddr4_s_axi_awaddr
    .c0_ddr4_s_axi_awlen            (axi4_m1_awlen              ), // input wire [7 : 0] c0_ddr4_s_axi_awlen
    .c0_ddr4_s_axi_awsize           (axi4_m1_awsize             ), // input wire [2 : 0] c0_ddr4_s_axi_awsize
    .c0_ddr4_s_axi_awburst          (axi4_m1_awburst            ), // input wire [1 : 0] c0_ddr4_s_axi_awburst
    .c0_ddr4_s_axi_awlock           ('d0                        ), // input wire [0 : 0] c0_ddr4_s_axi_awlock
    .c0_ddr4_s_axi_awcache          ('d0                        ), // input wire [3 : 0] c0_ddr4_s_axi_awcache
    .c0_ddr4_s_axi_awprot           ('d0                        ), // input wire [2 : 0] c0_ddr4_s_axi_awprot
    .c0_ddr4_s_axi_awqos            ('d0                        ), // input wire [3 : 0] c0_ddr4_s_axi_awqos
    .c0_ddr4_s_axi_awvalid          (axi4_m1_awvalid            ), // input wire c0_ddr4_s_axi_awvalid
    .c0_ddr4_s_axi_awready          (axi4_m1_awready            ), // output wire c0_ddr4_s_axi_awready

    .c0_ddr4_s_axi_wdata            (axi4_m1_wdata              ), // input wire [511 : 0] c0_ddr4_s_axi_wdata
    .c0_ddr4_s_axi_wstrb            (axi4_m1_wstrb              ), // input wire [63 : 0] c0_ddr4_s_axi_wstrb
    .c0_ddr4_s_axi_wlast            (axi4_m1_wlast              ), // input wire c0_ddr4_s_axi_wlast
    .c0_ddr4_s_axi_wvalid           (axi4_m1_wvalid             ), // input wire c0_ddr4_s_axi_wvalid
    .c0_ddr4_s_axi_wready           (axi4_m1_wready             ), // output wire c0_ddr4_s_axi_wready

    .c0_ddr4_s_axi_bready           (axi4_m1_bready             ), // input wire c0_ddr4_s_axi_bready
    .c0_ddr4_s_axi_bid              (                           ), // output wire [3 : 0] c0_ddr4_s_axi_bid
    .c0_ddr4_s_axi_bresp            (axi4_m1_bresp              ), // output wire [1 : 0] c0_ddr4_s_axi_bresp
    .c0_ddr4_s_axi_bvalid           (axi4_m1_bvalid             )  // output wire c0_ddr4_s_axi_bvalid
);

axi_bram u0_axi_bram
(
    .s_aclk                         (clk_100m_g                 ), // input wire s_aclk
    .s_aresetn                      (rst_n                      ), // input wire s_aresetn

    .s_axi_arid                     (                           ), // input wire [3 : 0] s_axi_arid
    .s_axi_araddr                   (axi4_m2_araddr             ), // input wire [31 : 0] s_axi_araddr
    .s_axi_arlen                    (axi4_m2_arlen              ), // input wire [7 : 0] s_axi_arlen
    .s_axi_arsize                   (axi4_m2_arsize             ), // input wire [2 : 0] s_axi_arsize
    .s_axi_arburst                  (axi4_m2_arburst            ), // input wire [1 : 0] s_axi_arburst
    .s_axi_arvalid                  (axi4_m2_arvalid            ), // input wire s_axi_arvalid
    .s_axi_arready                  (axi4_m2_arready            ), // output wire s_axi_arready
    .s_axi_rid                      (                           ), // output wire [3 : 0] s_axi_rid
    .s_axi_rdata                    (axi4_m2_rdata              ), // output wire [31 : 0] s_axi_rdata
    .s_axi_rresp                    (axi4_m2_rresp              ), // output wire [1 : 0] s_axi_rresp
    .s_axi_rlast                    (axi4_m2_rlast              ), // output wire s_axi_rlast
    .s_axi_rvalid                   (axi4_m2_rvalid             ), // output wire s_axi_rvalid
    .s_axi_rready                   (axi4_m2_rready             ), // input wire s_axi_rready
                                          
    .s_axi_awid                     (                           ), // input wire [3 : 0] s_axi_awid
    .s_axi_awaddr                   (axi4_m2_awaddr             ), // input wire [31 : 0] s_axi_awaddr
    .s_axi_awlen                    (axi4_m2_awlen              ), // input wire [7 : 0] s_axi_awlen
    .s_axi_awsize                   (axi4_m2_awsize             ), // input wire [2 : 0] s_axi_awsize
    .s_axi_awburst                  (axi4_m2_awburst            ), // input wire [1 : 0] s_axi_awburst
    .s_axi_awvalid                  (axi4_m2_awvalid            ), // input wire s_axi_awvalid
    .s_axi_awready                  (axi4_m2_awready            ), // output wire s_axi_awready

    .s_axi_wdata                    (axi4_m2_wdata              ), // input wire [31 : 0] s_axi_wdata
    .s_axi_wstrb                    (axi4_m2_wstrb              ), // input wire [3 : 0] s_axi_wstrb
    .s_axi_wlast                    (axi4_m2_wlast              ), // input wire s_axi_wlast
    .s_axi_wvalid                   (axi4_m2_wvalid             ), // input wire s_axi_wvalid
    .s_axi_wready                   (axi4_m2_wready             ), // output wire s_axi_wready
    .s_axi_bid                      (                           ), // output wire [3 : 0] s_axi_bid
    .s_axi_bresp                    (axi4_m2_bresp              ), // output wire [1 : 0] s_axi_bresp
    .s_axi_bvalid                   (axi4_m2_bvalid             ), // output wire s_axi_bvalid
    .s_axi_bready                   (axi4_m2_bready             ), // input wire s_axi_bready

    .rsta_busy                      (                           ), // output wire rsta_busy
    .rstb_busy                      (                           )  // output wire rstb_busy
);

endmodule




